The present invention relates to semiconductor integrated circuits, and more particularly to a matching network connected to a bond pad of a chip.
Signal return loss is a problem that occurs at the interface between a chip containing an integrated circuit (hereinafter, a “chip”) and a package to which it is mounted. Such loss can be substantial for radio frequency signals as the frequency of the signals increase. However, the connection of an appropriate matching network to bond pads of the chip, such as to C4 (“controlled collapse chip connection”) type bond pads can address the problem. The difficulty then becomes the construction of an appropriate matching network.
Such matching networks typically include passive devices such as inductors and capacitors having sizes that are sometimes close to that of the bond pads. For example, a bridged T-Coil matching network described in the article by L. Selmi et al., entitled “Small-Signal MMIC Amplifiers with Bridged T-Coil Matching Networks,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 7, July 1992, pp. 1093-1096, includes a pair of series-connected inductors. A T-coil provides a two-pole matching characteristic. With a matching network having a properly selected coil size, a high reactive impedance that would otherwise be present at the input gate of a signal receiver can be transformed to a constant, real 50 ohm termination resistance.
By integrating digital and analog circuits on the same semiconductor chip, especially a silicon chip, noise generated by digital circuits having large swing signals, e.g., rail-to-rail swing signals, is easily coupled into more sensitive analog circuits. The impact is felt especially for analog circuits which receive or output reduced swing signals, i.e., those which do not swing from rail to rail. In addition, as discussed in the article by R. C. Frye entitled “Integration and Electrical Isolation in CMOS Mixed Signal Wireless Chips,” Proc. of IEEE, vol. 89, No. 4, April 2001, pp. 444-455, there is an inherent conflict between the design factors involved in fabricating high quality factor (hereinafter, “Q”) passive components, and the design factors involved in providing robust electrical isolation for high Q components.
To increase the Q of an inductor, design considerations prefer the inductor to be disposed over a thick cavity area. However, a thick cavity area may not be possible in view of a particular structure required to avoid a circuit problem known as latch-up. For that purpose, the wafer structure usually includes a thin (i.e., having a few microns thickness) resistive epitaxial layer grown on top of a ground plate formed by a high conductivity bulk substrate region. In such case, the epitaxial layer is too thin to permit a high Q factor to be achieved for an on-chip inductor. However, unfortunately, the epitaxial layer cannot be simply thickened, because it will result in poorer electromagnetic isolation.
The article by J. Y. C. Chang et al. entitled “Large Suspended Inductors On Silicon and Their Use in a 2 μm CMOS RF Amplifier,” IEEE Electron Device Lett., Vol. 14, May 1993, pp. 146-248 proposed to improve the Q of the inductor by etching the bulk layer from underneath the inductor. However, the process disclosed therein is complex, and may fall short in terms of long-term reliability. Another proposed method of improving the Q of an on-chip spiral inductor includes a patterned ground shield, as described in the article by C. P. Yue et al. entitled “On-chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's,” IEEE Journal of Solid State Circuits, Vol. 33, No. 5, May 1998, pp. 743-752. It was noted such ground shield can not effectively improve the Q due to the increased parasitic capacitance of such ground shield.
In addition, a method proposed to improve the isolation of a wire bonding pad is described in the article by S. Lam et al., entitled “High-isolation Bonding Pad with Depletion-insulation Structure for RF/Microwave Integrated Circuit on Bulk Silicon CMOS,” 2002 IEEE MTT-S Digest, pp. 677-680. Here, as illustrated in the prior art FIG. 1, a p-type semiconductor diffusion region 10 is disposed inside an n-type well 11 provided in the semiconductor region 20 under the bond pad 12, in order to form depletion regions 15 for reducing the parasitic capacitance between the pad and the bulk region of the substrate, to reduce loss at the interface to the substrate. To further decrease the loss, that article also proposes that insulating oxide layers 22 be provided on top of the depletion structure underlying the bond pad 12. The structure is shown having a bond wire 14 bonded to the bond pad 12, and having a bulk region 20 of the substrate grounded through substrate contacts 24.
It is known to place circuit elements such as electro-static discharge protection (ESD) devices underneath a bond pad of a chip, as described in the article by H. G. Feng et al., entitled “Circular Under-Pad Multiple-mode ESD Protection Structure for ICs,” Electronics Letters, 23 May 2002, Vol. 38, No. 11, p. 511-513. Other discrete devices such as decoupling capacitors can also be placed underneath the pad. Technically, there is no reliability concern to place such devices under C4 type bond pads, since C4 bond pads are formed and interconnected to the package by processing involving relatively low physical force.
In view of the foregoing, it is seen that the state of the art regarding the design of an on-chip matching network depends upon the component values of reactive passive components such as inductors and the Q factors that can be achieved. The size of a reactive passive component such as an inductor is mainly determined by the inductor's component value. Such components scale inversely with frequency, i.e., the required component size can be made smaller as the signal frequency is increased. However, as a practical matter, the fabrication of on-chip inductor components must still conform to basic constraints. The linewidth of conductors used in such inductors varies little from one generation to the next. Accordingly, the overall dimensions of the inductor may either stay the same or decrease from one generation to the next. This is a major reason why the size of RF analog chips remains nearly constant despite new generations of transistor technology which enable operation at higher frequencies. The motivation of mixing analog circuits with digital circuits is to cut down the overall integration cost. Ultimately, the successfulness of mixed signal ICs depends on the ability to reduce the overall chip size. For that reason, there is a current need to pack large-sized analog components into a small chip area without jeopardizing the quality factor of the discrete analog components, while also avoiding high substrate loss. A second need exists to address the effect of semiconductor substrate loss on the effectiveness of T-coils as inductive components of a matching network.